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| ZL10100 Single Chip Synthesised Downconverter with IF Amplifier Data Sheet Features * Single chip synthesised downconverter forming a complete double conversion tuner when combined with the SL2100 or SL2101 Compatible with digital and analogue system requirements CTB contribution < -64 dBc, CXM contribution < -62 dBc and spectral spread < -64 dBc IF amplifier optimised to interface with standard SAW filters Extremely low phase noise balanced local oscillator with I2C bus controlled band switching and with very low fundamental and harmonic radiation Integral fast mode compliant I2C bus controlled PLL frequency synthesiser designed for high comparison frequencies and low phase noise performance Full ESD protection. (Normal ESD handling procedures should be observed) Double conversion tuners Digital Terrestrial tuners Cable Modems Data transmit systems Data communications systems MATV RF Input RF InputB IF Output IF OutputB DS5736 Issue 1.4 July 2002 Ordering Information ZL10100/DDA ZL10100/DDB (Tubes) (Tape & Reel) * * * * -40C to 85C Description The ZL10100 is a fully integrated single chip mixer oscillator with on-board low phase noise I2C bus controlled PLL frequency synthesiser. It is intended primarily as the down converter for application in double conversion tuners and is compatible with HIIF frequencies between 1 and 1.3 GHz and all standard tuner IF output frequencies. The device contains all elements necessary, with the exception of local oscillator tuning network, loop filter and crystal reference to fabricate a complete synthesised block converter with IF amplifier, compatible with digital and analogue requirements. * * Applications * * * * * * LO LOB VCO 15 Bit Programmable Divider Charge Pump fpd/ 2 Pump Drive SDA SCL ADD XTAL XTALCAP REF OSC I2C Bus Interface Fpd/2 Reference Divider Fcomp Port P0 Figure 1 - ZL10100 Functional Block Diagram SEMICMF.017 1 ZL10100 Pin Description IFOUTPUTB Vee VccRF Vee RFINPUTB RFINPUT Vee Vee VccD Vee SCL SDA XTAL XTAL CAP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 IFOUTPUT Vee VccIF Vee VccLO LO LOB VccLO Vee ADD Vee Port P0 DRIVE PUMP Data Sheet Figure 2 - Pin Description Quick Reference Data All data applies with the following conditions unless otherwise stated; a) Output load of 150 , differential b) Input spectrum of 5 channels centred on 1220 MHz, each carrier @ 77 dBV Characteristic RF input operating range IF output operating range Input noise figure, SSB Conversion gain, diff to diff CTB CXM Spectral spread Local oscillator phase noise SSB @ 10 kHz offset SSB @ 100 kHz offset Local oscillator phase noise floor IF output impedance, differential PLL phase noise at phase detector, 1 MHz comparison frequency 1-1.3 30-60 9 24 < -66 < -63 < -70 c -93 c-115 -136 150 -152 Units GHz MHz dB dB dBc dBc dBc dBc/Hz dBc/Hz dBc/Hz dBc/Hz 2 SEMICMF.017 Data Sheet 1.0 Functional Description ZL10100 The ZL10100 is a bipolar, broadband wide dynamic range mixer oscillator with on-board I2C bus controlled PLL frequency synthesiser, optimised for application as the down converter in double conversion tuner systems. It also has application in any system where a wide dynamic range broadband synthesised frequency converter is required. The ZL10100 is a single chip solution containing all necessary active circuitry and simply requires an external tuneable resonant network for the local oscillator sustaining network. The pin assignment is contained in the the block diagram in Figure 1 and the Pin Description in Figure 2. 1.1 Converter section In normal application the HIIF input is interfaced through appropriate impedance matching to the device input. The RF input preamplifier of the device is designed for low noise figure, within the operating region of 1 to 1.3 GHz and for high intermodulation distortion intercept so offering good signal to noise plus composite distortion spurious performance when loaded with a multi carrier system. The preamplifier also provides gain to the mixer section and back isolation from the local oscillator section. The typical RF input impedance and matching network for matching to a 1220 MHz HIIF filter, type B1603 are contained in Figures 3 and 4. The output of the preamplifier is fed to the mixer section which is optimised for low radiation application. In this stage the RF signal is mixed with the local oscillator frequency, which is generated by the on-board oscillator. The oscillator block uses an external tuneable network and is optimised for low phase noise. The typical application is shown in Figure 5, and the phase noise performance in Figure 6. This block interfaces direct with the internal PLL to allow for frequency synthesis of the local oscillator. The output of the mixer is internally coupled to a differential IF amplifier, which provides further gain and provides for a 150 , differential output impedance and drive capability. The IF amplifier allows for IF frequencies between 30 and 60 MHz. The typical IF output impedance is contained in Figure 7. The typical key performance data at 5V Vcc and 25 deg C ambient are shown in the Quick Reference Data section on Page 2. 1.2 Local Oscillator To maximise the local oscillator phase noise performance, the application circuit as in Figure 5 must be carefully adhered to including the component type and manufacture where applicable, strip line dimension and board material. Any deviation from these parameters may adversely affect phase noise characteristics and so will require re-optimisation. 1.3 PLL frequency Synthesiser The PLL frequency synthesiser section contains all the elements necessary, with the exception of a reference frequency source and loop filter to control the oscillator, so forming a complete PLL frequency synthesised source. The device allows for operation with a high comparison frequency and is fabricated in high speed logic, which enables the generation of a loop with good phase noise performance. The LO signal from the oscillator drives an internal preamplifier, which provides gain and reverse isolation from the divider signals. The output of the preamplifier interfaces direct with the 15-bit fully programmable divider. The programmable divider is of MN+A architecture, where the dual modulus prescaler is 16/17, the A counter is 4-bits, and the M counter is 11 bits. The output of the programmable divider is fed to the phase comparator where it is compared in both phase and frequency domain with the comparison frequency. This frequency is derived either from the on-board crystal controlled oscillator or from an external reference source. In both cases the reference frequency is divided down to the comparison frequency by the reference divider which is programmable into 1 of 29 ratios as detailed in Table 1. The typical application for the crystal oscillator is contained in Figure 8 which also demonstrates how a 4 MHz reference signal can be coupled out to a further PLL frequency synthesiser, such as the upconverter section in a double conversion tuner. SEMICMF.017 3 ZL10100 Data Sheet The output of the phase detector feeds a charge pump and loop amplifier, which when used with an external loop filter and high voltage transistor, integrates the current pulses into the varactor line voltage, used for controlling the oscillator. The programmable divider output Fpd divided by two and the reference divider output Fcomp can be switched to port P0 by programming the device into test mode. The test modes are described in Table 2. 2.0 Programming The ZL10100 is controlled by an I2C data bus and is compatible with both standard and fast mode formats. Data and Clock are fed in on the SDA and SCL lines respectively as defined by I2C bus format. The device can either accept data (write mode), or send data (read mode). The LSB of the address byte (R/W) sets the device into write mode if it is low, and read mode if it is high. Tables 3, 4 and 5 illustrate the format of the data. The device can be programmed to respond to several addresses, which enables the use of more than one device in an I2C bus system. Table 5 shows how the address is selected by applying a voltage to the 'ADD' input. When the device receives a valid address byte, it pulls the SDA line low during the acknowledge period, and during following acknowledge periods after further data bytes are received. When the device is programmed into read mode, the controller accepting the data must pull the SDA line low during all status byte acknowledge periods to read another status byte. If the controller fails to pull the SDA line low during this period, the device generates an internal STOP condition, which inhibits further reading. 2.1 Write mode With reference to Table 5, bytes 2 and 3 contain frequency information bits 214-20 inclusive. Byte 4 controls the synthesiser reference divider ratio, see Table 1 and the charge pump setting, see Table 6. Byte 5 controls the test modes, see Table 2 and the output port P0. After reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines whether the byte is interpreted as a byte 2 or 4, a logic '0' indicating byte 2, and a logic '1' indicating byte 4. Having interpreted this byte as either byte 2 or 4 the following data byte will be interpreted as byte 3 or 5 respectively. Having received two complete data bytes, additional data bytes can be entered, where byte interpretation follows the same procedure, without re-addressing the device. This procedure continues until a STOP condition is received. The STOP condition can be generated after any data byte, if however it occurs during a byte transmission, the previous byte data is retained. To facilitate smooth fine tuning, the frequency data bytes are only accepted by the device after all 15 bits of frequency data have been received, or after the generation of a STOP condition. 2.2 Read mode When the device is in read mode, the status byte read from the device takes the form shown in Table 4. Bit 1 (POR) is the power-on reset indicator, and this is set to a logic '1' if the Vcc supply to the device has dropped below 3V (at 25C), e.g., when the device is initially turned ON. The POR is reset to '0' when the read sequence is terminated by a STOP command. When POR is set high this indicates that the programmed information may have been corrupted and the device reset to the power up condition. Bit 2 (FL) indicates whether the synthesiser is phase locked, a logic '1' is present if the device is locked, and a logic '0' if the device is unlocked. 4 SEMICMF.017 Data Sheet Programmable Features Synthesiser programmable divider Reference programmable divider Charge pump current Test mode General purpose ports, P0 ZL10100 Function as described above. Function as described above. The charge pump current can be programmed by bits C1 and C0 within data byte 4, as defined in Table 6. The test modes are defined by bits T2-T0 as described in Table 2. The general purpose port can be programmed by bits P0; Logic '1' = on Logic '0' = off (high impedance) 26 Jun 2002 14:18:23 -74.777 2.1284 pF 1 000.000 000 MHz 2_: 29.262 -66.289 1.1 GHz 3_: 24.57 -58.744 1.22 GHz 4_: 22.332 -54.303 1.3 GHz CH1 S 11 1 U FS B1 4.7V 1_: 33.309 PRm Cor Avg 16 Smo Z0 50 1 43 2 START 1 000.000 000 MHz STOP 1 300.000 000 MHz Figure 3 - Typical RF input impedance 6 2.7 pF B1603 8.2 nH 2.7 pF 5 5 ZL10100 6 Figure 4 - RF input impedance matching network to B1603 HIIF filter SEMICMF.017 5 ZL10100 Data Sheet 23 22 1k 4.3 nH 2 pF Varactor line BB555 Figure 5 - Oscillator Application Phase noise (@ 10KHz offset), dBc -80 -85 -90 -95 -100 -105 -110 1010 1060 1110 LO Frequency (MHz) 1160 1210 Figure 6 - Typical phase noise performance with application as in Figure 5 6 SEMICMF.017 Data Sheet ZL10100 CH1 S 11 1 U FS B1 PIN1 4.7V 1_: 76.695 25 Jun 2002 06:58:03 -5.6172 944.45 pF 30.000 000 MHz 2_: 75.914 -7.2539 44 MHz 3_: 75.391 -7.9023 50 MHz 4_: 74.152 -9.207 60 MHz PRm Cor Avg 16 Smo Z0 75 1 2 3 4 START 30.000 000 MHz STOP 60.000 000 MHz Figure 7 - Typical IF output impedance single-ended SEMICMF.017 7 ZL10100 R4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R3 R2 R1 R0 Ratio 0 0 0 0 2 0 0 0 1 4 0 0 1 0 8 0 0 1 1 16 0 1 0 0 32 0 1 0 1 64 0 1 1 0 128 0 1 1 1 256 1 0 0 0 Illegal state 1 0 0 1 5 1 0 1 0 10 1 0 1 1 20 1 1 0 0 40 1 1 0 1 80 1 1 1 0 160 1 1 1 1 320 0 0 0 0 Illegal state 0 0 0 1 6 0 0 1 0 12 0 0 1 1 24 0 1 0 0 48 0 1 0 1 96 0 1 1 0 192 0 1 1 1 384 1 0 0 0 Illegal state 1 0 0 1 7 1 0 1 0 14 1 0 1 1 28 1 1 0 0 56 1 1 0 1 112 1 1 1 0 224 1 1 1 1 448 Table 1. Reference Division Ratios Data Sheet XTALCAP 47 pF 47 pF 4 MHz 10 pF Reference frequency output XTAL Figure 8 - Crystal oscillator application 8 SEMICMF.017 Data Sheet T2 0 0 0 0 1 1 1 1 T1 0 0 1 1 0 0 1 1 T0 0 1 Test Mode Description Normal operation Charge pump sink* Status byte FL set to logic '0' 0 Charge pump source* Status byte FL set to logic '0' 1 Charge pump disabled* Status byte FL set to logic '1' 0 Normal operation and Port P0 = Fpd/2 0 Charge pump sink* Status byte FL set to logic '0' Port P0 = Fcomp 0 Charge pump source* Status byte FL set to logic '0' Port P0 = Fcomp 1 Charge pump disabled* Status byte FL set to logic '1' Port P0 = Fcomp Table 2. Test modes ZL10100 * clocks need to be present on crystal and local oscillator to enable charge pump test modes and to toggle status byte bit FL Address Programmable divider Programmable divider Control data Control data MSB 1 1 0 214 27 26 1 C1 T2 T1 Table 3. Write data LSB 0 0 0 MA1 MA0 0 213 212 211 210 29 28 25 24 23 22 21 20 C0 R4 R3 R2 R1 R0 T0 X X X 0 P0 format (MSB is transmitted first) A A A A A Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Address Status Byte MSB LSB 1 1 0 0 0 MA1 MA0 1 POR FL 0 0 0 0 0 0 Table 4. Read data format (MSB is transmitted first) A A Byte 1 Byte 2 A : MA1,MA0 : 214-20 C1-C0 R4-R0 T2-T0 P0 POR FL X : : : : : : : : Acknowledge bit Variable address bits (see Table 5) Programmable division ratio control bits Charge pump current select (see Table 6) Reference division ratio select (seeTable 1) Test mode control bits (see Table 2) P0 port output state Power on reset indicator Phase lock flag 'Don't care' MA1 0 0 1 1 MA0 0 1 0 1 Address Input Voltage Level 0-0.1 Vcc Open circuit 0.4Vcc - 0.6 Vcc # 0.9 Vcc - Vcc Table 5. Address selection # Programmed by connecting a 30 k resistor between pin and Vcc SEMICMF.017 9 ZL10100 C1 0 0 1 1 min typ max 0 98 130 162 1 210 280 350 0 450 600 750 1 975 1300 1625 Table 6. Charge pump current C0 Current in A Data Sheet Electrical Characteristics - Test conditions (unless otherwise stated) Tamb = -40C to 85C, Vee= 0V, Vcc=5V5%. Input frequency 1220 MHz. IF output frequency 44 MHz. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Characteristic Supply current Input frequency range Composite peak input signal Input impedance Input Noise Figure Conversion gain Pin Min Typ 120 Max 160 1.3 Units mA GHz dBV Conditions 1 86 Operating condition only. See Figure 3. 9 20 23 11 26 dB dB Tamb = 27C Differential to differential voltage gain to differential 150 load. Channel bandwidth 8 MHz within operating frequency range. Gain variation within channel 0.5 dB Through gain CTB CXM LO operating range 0.9 -30 -64 -62 1.6 dB dBc dBc GHz See note 4. See note 4. Maximum tuning range determined by application, see note (3), guaranteed by design. LO phase noise, SSB @ 10 kHz offset @ 100 kHz offset LO phase noise floor IF output frequency range IF output impedance IF output return loss All other spurs on IF Output 30 -94 -116 -90 -110 -136 60 See Figure 6. dBc/Hz Application as in Figure 5. dBc/Hz dBc/Hz Application as in Figure 5. MHz Single-ended. See Figure 7. See Figure 7, over operating range. Within channel bandwidth of 8 MHz. 75 -20 20 d dBV 10 SEMICMF.017 Data Sheet Electrical Characteristics - Test conditions (unless otherwise stated) ZL10100 Tamb = -40C to 85C, Vee= 0V, Vcc=5V5%. Input frequency 1220 MHz. IF output frequency 44 MHz. These characteristics are guaranteed by either production test or design. They apply within the specified ambient temperature and supply voltage unless otherwise stated. Characteristic SYNTHESISER SDA, SCL Input high voltage Input low voltage Input high current Input low current Leakage current Hysterysis SDA output voltage SCL clock rate Charge pump output current Charge pump drive output current Crystal frequency Recommended crystal series resistance External reference input frequency External reference drive level Phase detector comparison frequency Equivalent phase noise at phase detector Local oscillator programmable divider division ratio Reference division ratio Output port sink current leakage current Pin Min Typ Max Units Conditions 3 0 -10 0.4 5.5 1.5 10 10 0.4 0.6 400 3 10 A A A V V I2C 'Fast mode' compliant Input voltage = Vcc Input voltage = Vee Vcc=Vee Isink = 3 mA Isink = 6 mA V V V kHz nA mA See Table 6. Vpin = 2V Vpin = 0.7V See Figure 8 for application. 4 MHz parallel resonant crystal Sinewave coupled through 10 nF blocking capacitor Sinewave coupled through 10 nF blocking capacitor 0.5 2 10 2 0.2 20 200 20 0.5 4 MHz MHz Vpp MHz -152 -158 240 32767 SSB, within loop bandwidth dBc/Hz 2 MHz dBc/Hz 250 kHz See Table 1. 2 mA A 10 1 -0.5 See note 2. Vport = 0.7 Vport = Vcc See Table 5 Vin = Vcc Vin = Vee Address select Input high current Input low current mA mA Notes (1) When measuring from a 50 environment, the voltage step up transformation needs to be taken into account. (2) Port powers up in high impedance state. (3) To maximise phase noise the tuning range should be minimised and Q of resonator maximised. The application as in Figure 5 has a tuning range of 200 MHz. (4) Measured with 5 channels @ 77 dBuV centred on desired channel . SEMICMF.017 11 ZL10100 Absolute Maximum Ratings - All voltages are referred to Vee at 0V. Characteristic Supply voltage RF input voltage All I/O port DC offsets SDA, SCL DC offsets Storage temperature Junction temperature Package thermal resistance, chip to case Package thermal resistance, chip to case Power consumption at 5.25V ESD protection 3.5 -0.3 -0.3 -55 Min -0.3 Max 7 117 Vcc+0.3 6 150 150 20 80 700 Units V dBuV V V C C C/W C/W mW kV Vcc = Vee to 5.25V Differential Data Sheet Conditions Mil-std 883B method 3015 cat1 12 SEMICMF.017 Data Sheet vcc RFINPUTB 5 XTAL XTALCAP 13 14 ZL10100 RFINPUT 6 200A RF Inputs VREF 500K LO 23 500K Reference Oscillator VCC 500K SCL/SDA LOB 22 * ACK Oscillator Inputs VCC 75 75 IF Output IF OutputB 28 1 *On SDA only SDA/SCL (pins 12 and 11) PO 17 IF Outputs vcc 15 Output Port vcc Pump 120K ADD 220 16 Drive 19 40K Loop Amplifier ADD Input Figure 9 - Input and Output Interface Circuits SEMICMF.017 13 14 R306 C308 100pF BCW31 TR3011 47pF IC1 VCC ZL10100 R311 10K C309 470nF C311 R305 SDA 10R C132 10pF R308 SCL 10R C342 10pF SAW201 EPCOS B1603 SAW Filter C302 27pF 5 1 +27V R302 To Zarlink SL2101 Up converter XTAL pin (2) R307 24K C307 33nF C301 X301 10pF 4MHz 22K 1K C305 100nF C306 6.8nF C330 100nF R303 20K ZL10100 R200 33R C312 R304 2.5pF 1K L311 4n3H L312 10nH 6 2 VCC From Zarlink SL2101 Up converter IF output pin (14) L202 6.8nH VCC R202 300R C201 1pF L201 6.8nH R203 300R 15 16 17 18 19 20 21 22 23 24 25 26 27 28 PUMP DRIVE PORT P0 Vee ADD Vee VccLO LO B LO VccLO Vee VccLO Vee IF Output VCC XTAL CAP XTAL SDA SCL Vee VccD Vee Vee RF Input RF Input B Vee VccRF Vee IF Output B C310 14 13 47pF 12 11 10 VCC 9 8 7 6 5 VCC 4 3 2 C316 1 100nF D301 BB555 L303 3u9H C318 100nF C324 100nF C300 100nF 3u9H C303 27pF L306 Figure 10 - ZL10100 Evaluation Board Schematic 4,8 R201 33R From Zarlink SL2101 Up converter IF output pin (15) IF Output / Demodulator Input IF Output B / Demodulator Input Data Sheet SEMICMF.017 For more information about all Zarlink products visit our Web Site at www.zarlink.com Information relating to products and services furnished herein by Zarlink Semiconductor Inc. trading as Zarlink Semiconductor or its subsidiaries (collectively "Zarlink") is believed to be reliable. However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink. This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink's conditions of sale which are available on request. Purchase of Zarlink's I2C components conveys a licence under the Philips I2C Patent rights to use these components in an I2C System, provided that the system conforms to the I2C Standard Specification as defined by Philips. Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2002, Zarlink Semiconductor Inc. All Rights Reserved. TECHNICAL DOCUMENTATION - NOT FOR RESALE |
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